عنوان

Guide to computer processor architecture

ويژگيها

(eISBN)

شابک

9783031180231

شماره

E4447

زبان متن نوشتاري يا گفتاري و مانند آن

انگلیسی

عنوان اصلي

Guide to computer processor architecture

نام عام مواد

[electronic resources: book]

ساير اطلاعات عنواني

: a RISC-V approach, with high-level synthesis

نام نخستين پديدآور

/ Bernard Goossens

محل نشرو پخش و غیره

Cham, Switzerland

نام ناشر، پخش کننده و غيره

: Springer

تاریخ نشرو بخش و غیره

, 2023.

نام خاص و کميت اثر

1 online resource

عنوان فروست

Undergraduate topics in computer science

متن يادداشت

Includes bibliographical references and index.

متن يادداشت

Part I. Single core processors -- 1. Getting Ready -- 2. Building a RISC-V Processor -- 3. Building a Pipelined RISC-V Processor -- 4. Building a RISC-V Processor with a Multi-cycle Pipeline -- 5. Building a RISC-V Processor with a Multiple Hart Pipeline -- Part II. Multiple core processors -- 6. Connecting IPs -- 7. A Multi-core RISC-V Processor -- 8. A Multi-core RISC-V Processor with Multi-hart Cores

بدون عنوان

0

متن يادداشت

This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Universite de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002

متن يادداشت

PDF file.

عنصر شناسه ای

Computer architecture

عنصر شناسه ای

RISC microprocessors

داده رابط بین فیلدها

a04

داده رابط بین فیلدها

a06

مستند نام اشخاص تاييد نشده

Goossens, Bernard, author.

کشور

Iran

سازمان

University of Tehran. Library of College of Science

تاريخ و ساعت مذاکره و دسترسي

UT_SCI_BL_DB_1004822_0001.pdf

فرمت انتشار

e

نوع ماده

BL

کد کاربرگه

278840

پیشوند ISBD اعمال شده است

1

سطح دسترسي

a

تكميل شده

Y