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عنوان
Logic synthesis and verification algorithms
پدید آورنده
/ Gary Hachtel, Fabio Somenzi
موضوع
Computer-aided design,Integrated circuits -- Verification,Logic design -- Data processing
رده
TK
7874
.
75
.
H33
2006
کتابخانه
Library of Campus2 Colleges of Engineering of Tehran University
محل استقرار
استان:
Tehran
ـ شهر:
Tehran
تماس با کتابخانه :
88225387
-
021
INTERNATIONAL STANDARD BOOK NUMBER
Qualification
(ebook)
(Number (ISBN
9780387310046
(Number (ISBN
0387310045
(Number (ISBN
0306475928
NATIONAL BIBLIOGRAPHY NUMBER
Country Code
IR
Number
45430
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
انگلیسی
COUNTRY OF PUBLICATION OR PRODUCTlON
Country of publication
IR
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Logic synthesis and verification algorithms
General Material Designation
[Book]
First Statement of Responsibility
/ Gary Hachtel, Fabio Somenzi
EDITION STATEMENT
Edition Statement
1st ed
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
New York
Name of Publisher, Distributor, etc.
: Springer
Date of Publication, Distribution, etc.
, 2006
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xxxii, 564 p.
Other Physical Details
: ill
Dimensions
; 23 cm
GENERAL NOTES
Text of Note
English
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
Includes bibliographical references (p.537-553) and index
TOPICAL NAME USED AS SUBJECT
Computer-aided design
Integrated circuits -- Verification
Logic design -- Data processing
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7874
.
75
Book number
.
H33
2006
PERSONAL NAME - PRIMARY RESPONSIBILITY
Hachtel, Gary, author
ORIGINATING SOURCE
Country
Iran
Agency
University of Tehran. Library of Technical Camp 2
Old cataloging
p
BL
1
Y
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