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عنوان
VHDL for logic synthesis
پدید آورنده
Rushton, Andrew
موضوع
، VHDL )Computer hardware description language(,Data processing ، Logic design,، Computer-aided design,، COMPUTERS / Computer Engineering
رده
TK
7885
.
7
.
R87
کتابخانه
Central Library of Hamedan University of Technology
محل استقرار
استان:
Hamedan
ـ شهر:
Hamedan
تماس با کتابخانه :
38411100
-
081
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
eng
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
VHDL for logic synthesis
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Chichester, West Sussex, U.K.
Name of Publisher, Distributor, etc.
Wiley
Date of Publication, Distribution, etc.
2011
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xvi, 466 p. : ill. ; 26 cm.
GENERAL NOTES
Text of Note
Includes bibliographical references and index
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
Andrew Rushton
ORIGINAL VERSION NOTE
Text of Note
1
TOPICAL NAME USED AS SUBJECT
Entry Element
، VHDL )Computer hardware description language(
Entry Element
Data processing ، Logic design
Entry Element
، Computer-aided design
Entry Element
، COMPUTERS / Computer Engineering
DEWEY DECIMAL CLASSIFICATION
Number
621
.
39/5
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7885
.
7
.
R87
PERSONAL NAME - PRIMARY RESPONSIBILITY
Entry Element
Rushton, Andrew
Relator Code
AU
TI
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