INTERNATIONAL STANDARD BOOK NUMBER
(Number (ISBN
9781461432692
NATIONAL BIBLIOGRAPHY NUMBER
Country Code
IR
Number
EN-57604
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
انگلیسی
COUNTRY OF PUBLICATION OR PRODUCTlON
Country of publication
IR
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Constraining Designs for Synthesis and Timing Analysi
General Material Designation
[Book]
Other Title Information
:A Practical Guide to Synopsys Design Constraints (SDC)
First Statement of Responsibility
/ by Sridhar Gangadharan, Sanjay Churiwala
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
New York, NY
Name of Publisher, Distributor, etc.
: Springer New York :Imprint: Springer,
Date of Publication, Distribution, etc.
, 2013.
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
XXVII, 226 p. 116 illus., online resource.
NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.
Text of Note
Electronic
CONTENTS NOTE
Text of Note
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. ? Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints; ? Includes key topics of interest to a synthesis, static timing analysis or place and route engineer; ? Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing; ? Explains fundamental concepts and provides exact command syntax.
Text of Note
Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC.
TOPICAL NAME USED AS SUBJECT
Engineering
Computer science
Electronics
Systems engineering
Electronic books
LIBRARY OF CONGRESS CLASSIFICATION
Class number
E-BOOK
PERSONAL NAME - PRIMARY RESPONSIBILITY
Gangadharan, Sridhar.
PERSONAL NAME - SECONDARY RESPONSIBILITY
Churiwala, Sanjay
SpringerLink (Online service)
ORIGINATING SOURCE
Country
ایران
ELECTRONIC LOCATION AND ACCESS
Host name
9781461432685.pdf
Access number
عادی
Compression information
عادی
Date and Hour of Consultation and Access
9781461432685.pdf
Electronic Format Type
متن
old catalog
e
BL
1
a
Y
