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عنوان
Source-synchronous networks-on-chip

پدید آورنده
/ Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra

موضوع
Networks on a chip, Design,Engineering,Circuits and Systems,Processor Architectures,Electronics and Microelectronics, Instrumentation,TECHNOLOGY & ENGINEERING / Mechanical, bisacsh

رده
E-BOOK

کتابخانه
Central Library, Center of Documentation and Supply of Scientific Resources

محل استقرار
استان: East Azarbaijan ـ شهر:

Central Library, Center of Documentation and Supply of Scientific Resources

تماس با کتابخانه : 04133443834

INTERNATIONAL STANDARD BOOK NUMBER

(Number (ISBN
9781461494041

NATIONAL BIBLIOGRAPHY NUMBER

Country Code
IR
Number
EN-57491

LANGUAGE OF THE ITEM

.Language of Text, Soundtrack etc
انگلیسی

COUNTRY OF PUBLICATION OR PRODUCTlON

Country of publication
IR

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
Source-synchronous networks-on-chip
General Material Designation
[Book]
Other Title Information
:circuit and architectural interconnect modeling
First Statement of Responsibility
/ Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
New York
Name of Publisher, Distributor, etc.
: Springer,
Date of Publication, Distribution, etc.
, 2014.

NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.

Text of Note
Electronic

INTERNAL BIBLIOGRAPHIES/INDEXES NOTE

Text of Note
Includes bibliographical references and index..

CONTENTS NOTE

Text of Note
Summary: This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. Describes novel methods for high-speed network-on-chip (NoC) design; Enables readers to understand NoC design from both circuit and architectural levels; Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.
Text of Note
Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work.

TOPICAL NAME USED AS SUBJECT

Networks on a chip, Design
Engineering
Circuits and Systems
Processor Architectures
Electronics and Microelectronics, Instrumentation
TECHNOLOGY & ENGINEERING / Mechanical, bisacsh

LIBRARY OF CONGRESS CLASSIFICATION

Class number
E-BOOK

PERSONAL NAME - SECONDARY RESPONSIBILITY

Mandal, Ayan
Khatri, Sunil P.,1965-
Mahapatra, Rabi N

ORIGINATING SOURCE

Country
ایران

ELECTRONIC LOCATION AND ACCESS

Host name
9781461494041.pdf
Access number
عادی
Compression information
عادی
Date and Hour of Consultation and Access
9781461494041.pdf
Electronic Format Type
متن

old catalog

e

BL
1

a
Y

Proposal/Bug Report

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