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عنوان
timing simulation and the degradation delay model-Logic

پدید آورنده

موضوع
Timing circuits. ; Integrated circuits ; Very large scale integration. ; Metal oxide semiconductors, Complementary. ;

رده

کتابخانه
Central Library and Documents Center of Mazandaran University

محل استقرار
استان: Mazandaran ـ شهر: Babolsar

Central Library and Documents Center of Mazandaran University

تماس با کتابخانه : 62-35302861-011

NATIONAL BIBLIOGRAPHY NUMBER

Number
oldebook18652

LANGUAGE OF THE ITEM

.Language of Text, Soundtrack etc
eng

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
timing simulation and the degradation delay model-Logic

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
London :
Name of Publisher, Distributor, etc.
: Imperial College Press,
Date of Publication, Distribution, etc.
, 2006.

NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.

Text of Note
Print

TOPICAL NAME USED AS SUBJECT

Timing circuits. ; Integrated circuits ; Very large scale integration. ; Metal oxide semiconductors, Complementary. ;

PERSONAL NAME - PRIMARY RESPONSIBILITY

; Juan Chico, Jorge. ; Valencia, Manuel. ; -Bellido, Manuel J., ; 1964

old catalog

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