عنوان

Built-in self test logic for a histogrammer memory chip

Number

TLpq230948157

.Language of Text, Soundtrack etc

انگلیسی

Title Proper

Built-in self test logic for a histogrammer memory chip

General Material Designation

[Thesis]

First Statement of Responsibility

A. A. Hamzah

Name of Publisher, Distributor, etc.

King Fahd University of Petroleum and Minerals (Saudi Arabia)

Date of Publication, Distribution, etc.

1993

Specific Material Designation and Extent of Item

94

Dissertation or thesis details and type of degree

M.S.

Body granting the degree

King Fahd University of Petroleum and Minerals (Saudi Arabia)

Text preceding or following the note

1993

Text of Note

Memories, being an important part of most digital systems, should be properly tested. The testing time of these memories is a major concern since its cost constitutes a large percentage of the total cost. Histogrammer memory chips (HRAMs) are commonly used in digital image processing and also widely used for on-line sorting of data in nuclear physics experiments and in medical imaging systems. This research investigates the testability problem of a histogrammer memory chip (HRAM) being designed at KFUPM. A general fault model for the HRAM is adopted and new design for testability features are identified. Efficient O() test procedures for both the memory array and decoders of the KRAM are described (n is the number of memory cells). The testability features area overhead is only O(log n) as compared to O() for previous approaches. Random Built-In Self Test (BIST) implementation of the array and decoder test algorithms is described in detail.

Applied sciences

Computer science

Electrical engineering

A. A. Hamzah

Electronic name

p

[Thesis]

276903

a

Y