عنوان

Timing performance of nanometer digital circuits under process variations /

(Number (ISBN

3030092399

(Number (ISBN

3319754653

(Number (ISBN

3319754661

(Number (ISBN

9783030092399

(Number (ISBN

9783319754659

(Number (ISBN

9783319754666

Erroneous ISBN

3319754645

Erroneous ISBN

9783319754642

Title Proper

Timing performance of nanometer digital circuits under process variations /

General Material Designation

[Book]

First Statement of Responsibility

Victor Champac, Jose Garcia Gervacio.

Place of Publication, Distribution, etc.

Cham, Switzerland :

Name of Publisher, Distributor, etc.

Springer,

Date of Publication, Distribution, etc.

[2018]

Date of Publication, Distribution, etc.

©2018

Specific Material Designation and Extent of Item

1 online resource

Series Title

Frontiers in electronic testing ;

Volume Designation

Volume 39

Text of Note

Includes bibliographical references and index.

Text of Note

Intro; Preface; Contents; About the Authors; Acronyms; 1 Introduction; 1.1 Semiconductor Technology; 1.2 First Words of Process Variations on Semiconductor Technologies; 1.3 Making Modern Digital Circuits; 1.3.1 Nanometer Design; 1.3.2 Impact of Process Variation on Nanometer Design; 1.3.3 Corner-Based Nanometer Design; 1.4 Need of Statistical Circuit Design; References; 2 Mathematical Fundamentals; 2.1 Basic Definitions; 2.1.1 Definitions; 2.2 Random Variables; 2.2.1 Discrete Random Variables; 2.2.1.1 Probability Mass Function; 2.2.1.2 Cumulative Distribution Function.

Text of Note

2.2.2 Continuous Random Variables2.2.2.1 Probability Density Function; 2.2.2.2 Cumulative Distribution Function; 2.3 Characteristics of Random Variables; 2.3.1 Mean; 2.3.1.1 Discrete Variables; 2.3.1.2 Continuous Variables; 2.3.2 Variance; 2.3.2.1 Discrete Variables; 2.3.2.2 Continuous Variables; 2.4 Distributions of Random Variables; 2.4.1 Continuous Uniform Distribution; 2.4.2 Continuous Normal Distribution; 2.5 Relationship Properties of Random Variables; 2.5.1 Covariance; 2.5.1.1 Discrete Variables; 2.5.1.2 Continuous Variables; 2.5.2 Correlation; 2.6 Sum of Normal Random Variables.

Text of Note

2.6.1 Sum of Two Normal Random Variables2.6.1.1 Mean; 2.6.1.2 Variance; 2.6.2 Sum of More than Two Normal Random Variables; 2.6.2.1 Mean; 2.6.2.2 Variance; 2.7 Series and Theorem of Taylor; 2.7.1 Basic Definitions; 2.7.2 Single Variable; 2.7.3 Two Variables; 2.8 Summary; References; 3 Process Variations; 3.1 Introduction; 3.2 CMOS Manufacturing Process; 3.2.1 CMOS Technology Overview; 3.2.2 Main Manufacturing Processes; 3.2.2.1 Photolithography; 3.2.2.2 Etching; 3.2.2.3 Doping; 3.2.2.4 Deposition; 3.2.2.5 Planarization; 3.3 Sources of Process Variations.

Text of Note

3.3.1 Sources of Variation on Device Parameters3.3.1.1 Sources of Variation in the Channel Length; 3.3.1.2 Line Edge Roughness; 3.3.1.3 Optical Proximity Effect; 3.3.1.4 Sources of Variation in the Channel Width; 3.3.1.5 Sources of Variation in the Gate Oxide Thickness; 3.3.1.6 Sources of Variation in the Threshold Voltage; 3.3.1.7 Random Dopant Fluctuation; 3.3.2 Sources of Variation in Interconnections; 3.3.2.1 Chemical Mechanical Polishing; 3.4 Behavior of Process Parameter Variations; 3.4.1 Systematic; 3.4.2 Nonsystematic; 3.4.2.1 Inter-die Variations; 3.4.2.2 Intra-Die Variations.

Text of Note

3.5 Parameter Modeling3.6 Spatial Correlation Modeling; 3.6.1 Exponential Model; 3.6.1.1 Example; 3.6.2 Grid Model; 3.7 Summary; References; 4 Gate Delay Under Process Variations; 4.1 Mathematical Formulation of the Statistical Delay of a Logic Gate; 4.1.1 Mean Delay of a Gate; 4.1.2 Variance of the Delay of a Gate; 4.2 Delay of Logic Gates Under Process Variations; 4.3 Computing Delay Variance of an Inverter; 4.3.1 Analytical Delay Model; 4.3.2 Sensitivity Delay Model; 4.3.3 Example of Computing Delay Standard Deviation of an Inverter; 4.4 Computing Delay Variance of a Nand Gate.

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Text of Note

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level "design hints" are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.

Source for Acquisition/Subscription Address

Springer Nature

Stock Number

com.springer.onix.9783319754659

Title

Timing performance of nanometer digital circuits under process variations.

International Standard Book Number

9783319754642

Integrated circuits-- Design and construction.

Nanoelectronics-- Materials.

Radio circuits.

Circuits & components.

Computer architecture & logic design.

Electronics engineering.

Integrated circuits-- Design and construction.

Radio circuits.

TECHNOLOGY & ENGINEERING-- Mechanical.

TEC-- 009070

TJFC

TJFC

Number

Edition

Class number

Champac, Victor

Gervacio, Jose Garcia

Date of Transaction

20200823105938.0

Cataloguing Rules (Descriptive Conventions))

pn

Electronic name

[Book]

Y