عنوان

Algorithm-architecture matching for signal and image processing :

(Number (ISBN

9048199646

(Number (ISBN

9048199654

(Number (ISBN

9789048199648

(Number (ISBN

9789048199655

Number

b592151

Title Proper

Algorithm-architecture matching for signal and image processing :

General Material Designation

[Book]

Other Title Information

best papers from design and architectures for signal and image processing 2007 et 2008 et 2009

First Statement of Responsibility

Guy Gogniat ... eds.

Place of Publication, Distribution, etc.

Dordrecht

Name of Publisher, Distributor, etc.

Springer

Date of Publication, Distribution, etc.

2011

Series Title

Lecture notes in electrical engineering, 73.

Text of Note

Preface. Part 1: Architectures for embedded applications. Chapter 1: Architectures for image processing. Lossless Multi-mode Interband Image Compression and its Hardware Architecture. Efficient Memory Management for Uniform and Recursive Grid Traversal. Chapter 2: Architectures for signal and telecommunication processing. Mapping a Telecommunication Application on a Multiprocessor System-on-Chip. Part 2: Data acquisition and embedded systems. Chapter 3: Sensors for data acquisition. A Standard 3.5T CMOS Imager including a Light Adaptive System for Integration Time Optimization. Chapter 4: Operators for embedded systems. Approximate Multiplication and Division for Arithmetic Data Value Speculation in a RISC Processor. Chapter 5: Partial and dynamic reconfiguration for signal and image processing. RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip. A New three-Level Strategy for Off-line Placement of Hardware Tasks on Partially and Dynamically Reconfigurable Hardware. End-to-end Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. Part 3: Embedded systems design. Chapter 6: RTOS for embedded systems. SystemC multiprocessor RTOS model for services distribution on MPSoC platforms. Chapter 7: Scheduling of embedded systems. A List Scheduling Heuristic with New Node Priorities and Critical Child Technique for Task Scheduling with Communication Contention. Multiprocessor scheduling of dataflow programs within the Reconfigurable Video Coding framework. Chapter 8: CAD tools for signal and image processing. A High Level Synthesis Flow Using Model Driven Engineering. Generation of Hardware/Software systems based on CAL dataflow description.

Class number

Book number

Guy Gogniat ... eds.

Guy Gogniat

Electronic name

[Book]

Y