• Home
  • Advanced Search
  • Directory of Libraries
  • About lib.ir
  • Contact Us
  • History

عنوان
High Level Synthesis of ASICs under Timing and Synchronization Constraints

پدید آورنده
by David C. Ku, Giovanni Micheli.

موضوع
Computer engineering.,Computer-aided design.,Engineering.,Systems engineering.

رده

کتابخانه
Center and Library of Islamic Studies in European Languages

محل استقرار
استان: Qom ـ شهر: Qom

Center and Library of Islamic Studies in European Languages

تماس با کتابخانه : 32910706-025

INTERNATIONAL STANDARD BOOK NUMBER

(Number (ISBN
9781441951298
(Number (ISBN
9781475721171

NATIONAL BIBLIOGRAPHY NUMBER

Number
b402360

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
High Level Synthesis of ASICs under Timing and Synchronization Constraints
General Material Designation
[Book]
First Statement of Responsibility
by David C. Ku, Giovanni Micheli.

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
Boston, MA :
Name of Publisher, Distributor, etc.
Imprint: Springer,
Date of Publication, Distribution, etc.
1992.

SERIES

Series Title
Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing,
Volume Designation
177
ISSN of Series
0893-3405 ;

SUMMARY OR ABSTRACT

Text of Note
Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

OTHER EDITION IN ANOTHER MEDIUM

International Standard Book Number
9781441951298

PIECE

Title
Springer eBooks

TOPICAL NAME USED AS SUBJECT

Computer engineering.
Computer-aided design.
Engineering.
Systems engineering.

PERSONAL NAME - PRIMARY RESPONSIBILITY

Ku, David C.

PERSONAL NAME - ALTERNATIVE RESPONSIBILITY

Micheli, Giovanni.

CORPORATE BODY NAME - ALTERNATIVE RESPONSIBILITY

SpringerLink (Online service)

ORIGINATING SOURCE

Date of Transaction
20190301083100.0

ELECTRONIC LOCATION AND ACCESS

Electronic name
 مطالعه متن کتاب 

[Book]

Y

Proposal/Bug Report

Warning! Enter The Information Carefully
Send Cancel
This website is managed by Dar Al-Hadith Scientific-Cultural Institute and Computer Research Center of Islamic Sciences (also known as Noor)
Libraries are responsible for the validity of information, and the spiritual rights of information are reserved for them
Best Searcher - The 5th Digital Media Festival