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عنوان
Logic synthesis and verification algorithms

پدید آورنده
Hachtel, Gary D.

موضوع
، Integrated circuits-- Very large scale integration-- Design-- Data processing,، Logic design-- Data processing,، Integrated circuits-- Verification,، Computer-aided design

رده
TK
7874
.
75
.
H33
1996

کتابخانه
Central Library of Sharif University of Technology

محل استقرار
استان: Tehran ـ شهر: Tehran

Central Library of Sharif University of Technology

تماس با کتابخانه : 66005817-021

OTHER STANDARD IDENTIFIER

Standard Number
145239

LANGUAGE OF THE ITEM

.Language of Text, Soundtrack etc
تا‌بستا‌ن‌۷۸
.Language of Text, Soundtrack etc
English

TITLE AND STATEMENT OF RESPONSIBILITY

General Material Designation
)20(
First Statement of Responsibility
Hachtel, Gary D.
Title Proper
Logic synthesis and verification algorithms

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
Boston
Name of Publisher, Distributor, etc.
Kluwer Academic Publishers
Date of Publication, Distribution, etc.
1996

PHYSICAL DESCRIPTION

Specific Material Designation and Extent of Item
xxxii, 564 p.: ill.; 26 cm.

GENERAL NOTES

Text of Note
Includes bibliographical references and index

TOPICAL NAME USED AS SUBJECT

Entry Element
، Integrated circuits-- Very large scale integration-- Design-- Data processing
Entry Element
، Logic design-- Data processing
Entry Element
، Integrated circuits-- Verification
Entry Element
، Computer-aided design

LIBRARY OF CONGRESS CLASSIFICATION

Class number
TK
7874
.
75
.
H33
1996

PERSONAL NAME - PRIMARY RESPONSIBILITY

Relator Code
AU
Entry Element
by Gary D. Hachtel, Fabio Somenzi

AU oibaF ,iznemoS
TI

LOCATION AND CALL NUMBER

Shelving Form of Title, Author, Author/Title
02

Proposal/Bug Report

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