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عنوان
Formal semantics and proof techniques for optimizing VHDL models
پدید آورنده
Umamageswaran, Kothanda
موضوع
، VHDL )Computer hardware description language(
رده
TK
7885
.
7
.
U43
1999
کتابخانه
Central Library of Sharif University of Technology
محل استقرار
استان:
Tehran
ـ شهر:
Tehran
تماس با کتابخانه :
66005817
-
021
OTHER STANDARD IDENTIFIER
Standard Number
123183
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
زمستان۹۷
.Language of Text, Soundtrack etc
English
TITLE AND STATEMENT OF RESPONSIBILITY
General Material Designation
)20(
First Statement of Responsibility
Umamageswaran, Kothanda
1974-
Title Proper
Formal semantics and proof techniques for optimizing VHDL models
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boston
Name of Publisher, Distributor, etc.
Kluwer Academic Publishers
Date of Publication, Distribution, etc.
1999
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xvi, 158 p.: ill.; 25 cm
GENERAL NOTES
Text of Note
Includes bibliographical references and index
TOPICAL NAME USED AS SUBJECT
Entry Element
، VHDL )Computer hardware description language(
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7885
.
7
.
U43
1999
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
Entry Element
Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
AU .L uhsnateehS ,yednaP 1972-
AU .A pilihP ,yesliW 1958-
TI
LOCATION AND CALL NUMBER
Shelving Form of Title, Author, Author/Title
02
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