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عنوان
Verification and validation in systems engineering : assessing UML/SysML design models
پدید آورنده
موضوع
Systems engineering ► Expert systems (Computer science)- Verification ► UML (Computer science) ► SysML (Computer science) ► Systementwicklung ► UML ► SysML ► Software Engineering ► Softwaremetrie ► Programmanalyse ► Verifikation ► Validierung ► Leistungsbewertung
رده
V516
کتابخانه
Central Library and Document Center of Isfahan University
محل استقرار
استان:
Esfahan
ـ شهر:
Esfahan
تماس با کتابخانه :
031
-
031 و 37932186
-
37933185
INTERNATIONAL STANDARD BOOK NUMBER
(Number (ISBN
9783642152276
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Verification and validation in systems engineering : assessing UML/SysML design models
.PUBLICATION, DISTRIBUTION, ETC
Date of Publication, Distribution, etc.
c2010
Name of Publisher, Distributor, etc.
Heidelberg, New York : Springer
PHYSICAL DESCRIPTION
Other Physical Details
700BL0017098
Other Physical Details
xxvi, 248 p 24 cm
TOPICAL NAME USED AS SUBJECT
Entry Element
Systems engineering ► Expert systems (Computer science)- Verification ► UML (Computer science) ► SysML (Computer science) ► Systementwicklung ► UML ► SysML ► Software Engineering ► Softwaremetrie ► Programmanalyse ► Verifikation ► Validierung ► Leistungsbewertung
DEWEY DECIMAL CLASSIFICATION
Edition
V516
PERSONAL NAME - SECONDARY RESPONSIBILITY
Entry Element
Mourad Debbabi ... [et al.]
CORPORATE BODY NAME - SECONDARY RESPONSIBILITY
Entry Element
AU Debbabi, Mourad
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