عنوان
پدید آورنده
موضوع
رده
TK 7885.7 .C39S4
TK
7885
.
7
.
C39S4
کتابخانه
محل استقرار
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Sequentila logic and verilog HDL fundamentals
First Statement of Responsibility
Joseph Cavanagh
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boca Raton
Name of Publisher, Distributor, etc.
Taylor & Francis/CRC Press
Date of Publication, Distribution, etc.
2016
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xiv, 846 p: ill
GENERAL NOTES
Text of Note
ISBN: 9781498738224
ORIGINAL VERSION NOTE
Text of Note
1
TOPICAL NAME USED AS SUBJECT
Entry Element
، Verilog )Computer hardware description language(
Entry Element
، Logic design
Entry Element
، Sequential circuits
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7885
.
7
.
C39S4
PERSONAL NAME - PRIMARY RESPONSIBILITY
Entry Element
Cavanagh, Joseph J. F.
Relator Code
AU
