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عنوان
Fundamentals of digital logic with Verilog design

پدید آورنده
/ Stephen Brown and Zvonko Vranesic,Brown

موضوع
Logic circuits -- Design and construction -- Data processing,Verilog (Computer hardware description language),Computer - aided design

رده
TK
7868
.
L6B76

کتابخانه
Central Library and Documents Center of Tehran University

محل استقرار
استان: Tehran ـ شهر: Tehran

Central Library and Documents Center of Tehran University

تماس با کتابخانه : 66466179-61112362-021

INTERNATIONAL STANDARD BOOK NUMBER

(Number (ISBN
0-07-282315-1

NATIONAL BIBLIOGRAPHY NUMBER

Country Code
IR
Number
204439

LANGUAGE OF THE ITEM

.Language of Text, Soundtrack etc
فارسی

COUNTRY OF PUBLICATION OR PRODUCTlON

Country of publication
IR

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
Fundamentals of digital logic with Verilog design
General Material Designation
[Book]
First Statement of Responsibility
/ Stephen Brown and Zvonko Vranesic

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
Boston
Name of Publisher, Distributor, etc.
: McGraw - Hill
Date of Publication, Distribution, etc.
, c2003

PHYSICAL DESCRIPTION

Specific Material Designation and Extent of Item
xx, 844 p.
Other Physical Details
: ill; 25 cm
Accompanying Material
+ 1 CD-Rom (43/4)

GENERAL NOTES

Text of Note
فارسي
Text of Note
Offset in Iran by Nass pub. in 1383

INTERNAL BIBLIOGRAPHIES/INDEXES NOTE

Text of Note
Includes bibliographical references and index

TOPICAL NAME USED AS SUBJECT

Logic circuits -- Design and construction -- Data processing
Verilog (Computer hardware description language)
Computer - aided design

LIBRARY OF CONGRESS CLASSIFICATION

Class number
TK
7868
Book number
.
L6B76

PERSONAL NAME - PRIMARY RESPONSIBILITY

Entry Element
Brown
Part of Name Other than Entry Element
, Stephen D
Relator Code
, author

PERSONAL NAME - SECONDARY RESPONSIBILITY

Entry Element
Vranesic
Part of Name Other than Entry Element
, Zvonko G

ORIGINATING SOURCE

Country
Iran
Agency
Central Library Of Tehran University

Old cataloging

BL
1

Y

Proposal/Bug Report

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