عنوان
پدید آورنده
موضوع
رده
TK 7885.7 .S67
TK
7885
.
7
.
S67
کتابخانه
محل استقرار
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
System verilog for verification :a guide to learning the testbench language features
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
New York
Name of Publisher, Distributor, etc.
Springer
Date of Publication, Distribution, etc.
2008
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
p. cm.
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
Chris Spear
ORIGINAL VERSION NOTE
Text of Note
1
TOPICAL NAME USED AS SUBJECT
Entry Element
، Verilog )Computer hardware description language(
Entry Element
Verification ، Integrated circuits
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7885
.
7
.
S67
PERSONAL NAME - PRIMARY RESPONSIBILITY
Entry Element
Spear, Chris.
Relator Code
AU
TI
