INTERNATIONAL STANDARD BOOK NUMBER
(Number (ISBN
1402070683
NATIONAL BIBLIOGRAPHY NUMBER
Country Code
IR
Number
EN-55096
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
انگلیسی
COUNTRY OF PUBLICATION OR PRODUCTlON
Country of publication
IR
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Asynchronous pulse logic
General Material Designation
[Book]
First Statement of Responsibility
/ Mika Nystrom, Alain J. Martin
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boston
Name of Publisher, Distributor, etc.
: Kluwer Academic Publishers,
Date of Publication, Distribution, etc.
, c2002.
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xxv, 206 p. ill. 25 cm.
NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.
Text of Note
Electronic
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
ng
Text of Note
Includes bibliographical references (p. [195]-200) and index.
CONTENTS NOTE
Text of Note
Machine generated contents note: 1. PRELIMINARIES -- 1 High-speed CMOS-circuits -- 2 Asynchronous protocols and delay-insensitive codes -- 3 Production rules -- 4 The MiniMIPS processor -- 5 Commonly used abbreviations -- 2. ASYNCHRONOUS-PULSE-LOGIC BASICS -- 1 Road map of this chapter -- 2 The pulse repeater -- 2.1 Timing constraints in the pulse repeater -- 2.2 Simulating the pulse repeater -- 2.3 The synchronous digital model -- 2.4 Asymmetric pulse-repeaters -- 3 Formal model of pulse repeater -- 3.1 Basic definitions -- 3.2 Handling the practical simulations -- 3.3 Expanding the model -- 3.4 Using the extended model -- 3.5 Noise margins -- 4 Differential-equations treatment of pulse repeater -- 4.1 Input behavior of pulse repeater -- 3. COMPUTING WITH PULSES -- I A simple logic example -- 2 Pulse-handshake duty-cycle -- 3 Single-track-handshake interfaces -- 4 Timing constraints and timing "assumptions" -- 5 Minimum cycle-transition-counts -- 6 Solutions to transition-count problem -- 7 The APL design-style in short -- 4. A SINGLE-TRACK ASYNCHRONOUS-PULSE- -- LOGIC FAMILY: I. BASIC CIRCUITS -- 1 Preliminaries -- 1.1 Transition counting in pipelined asynchronous circuits -- 1.2 Transition-count choices in pulsed circuits -- 1.3 Execution model -- 1.4 Capabilities of the STAPL family -- 1.5 Design philosophy -- 2 The basic template -- 2.1 Bit generator -- 2.2 Bit bucket -- 2.3 Left-right buffer -- 3 Summary of properties of the simple circuits -- 5. A SINGLE-TRACK ASYNCHRONOUS-PULSE- -- LOGIC FAMILY: II. ADVANCED CIRCUITS -- 1 Multiple input and output channels -- 1.1 Naive implementation -- 1.2 Double triggering of logic block in the naive design -- 1.3 Solution -- 1.4 Timing assumptions -- 2 General logic computations -- 2.1 Inputs whose values are not used -- 3 Conditional communications -- 3.1 The same program can be expressed in several ways -- 3.2 Simple techniques for sends -- 3.3 General techniques for conditional communications -- 4 Storing state -- 4.1 The general state-storing problem -- 4.2 Implementing state variables -- 4.3 Compiling the state bit -- 5 Special circuits -- 5.1 Arbitration -- 5.2 Four-phase converters -- 6 Resetting STAPL circuits -- 6.1 Previously used resetting schemes -- 6.2 An example -- 6.3 Generating initial tokens -- 7 How our circuits relate to the design philosophy -- 8 Noise -- 8.1 External noise-sources -- 8.2 Charge sharing -- 8.3 Crosstalk -- 8.4 Design inaccuracies -- 6. AUTOMATIC GENERATION OF -- ASYNCHRONOUS-PULSE-LOGIC CIRCUITS -- 1 Straightforwardly compiling from a higher-level specification -- 2 An alternative compilation method -- 3 What we compile -- 4 The PL1 language -- 4.1 Channels or shared variables? -- 4.2 Simple description of the PL1 language -- 4.3 An example: the replicator -- 5 Compiling PLI -- 6 PL 1-compiler front-end -- 6.1 Determinism conditions -- 6.2 Data encoding -- 7 PL -compiler back-end -- 7.1 Slack -- 7.2 Logic simplification -- 7.3 Code generation -- 7. A DESIGN EXAMPLE: -- THE SPAM MICROPROCESSOR -- 1 The SPAM architecture -- 2 SPAM implementation -- 2.1 Decomposition -- 2.2 Arbitrated branch-delay -- 2.3 Byte skewing -- 3 Design examples -- 3.1 The PCUNIT -- 3.2 The REGFILE -- 4 Performance measurements on the SPAM implementation -- 4.1 Straightline program -- 4.2 Computing Fibonacci numbers -- 4.3 Energy measurements -- 4.4 Summary of SPAM implementation's performance -- 4.5 Comparison with QDI -- 8. RELATED WORK -- 1 Theory -- 2 STAPL circuit family -- 3 PL1 language -- 4 SPAM microprocessor -- 9. LESSONS LEARNED -- 1 Conclusion -- Appendices -- PL1 Report -- 0.1 Scope -- 0.2 Structure of PL1 -- 1 Syntax elements -- 1.1 Keywords -- 1.2 Comments -- 1.3 Numericals -- 1.4 Identifiers -- 1.5 Reserved special operators -- 1.6 Expression operators -- 1.7 Expression syntax -- 1.8 Actions -- 2 PL1 process description -- 2.1 Declarations -- 2.2 Communication statement -- 2.3 Process communication-block -- 3 Semantics -- 3.1 Expression semantics -- 3.2 Action semantics -- 3.3 Execution semantics -- 3.4 Invariants -- 3.5 Semantics in terms of CHP -- 3.6 Slack elasticity -- 4 Examples -- SPAM Processor Architecture Definition -- 1 SPAM overview -- 2 SPAM instruction format -- 3 SPAM instruction semantics -- 3.1 Operand generation -- 3.2 Operation definitions -- 4 Assembly-language conventions -- 4.1 The SPAM assembly format -- Proof that Definition 2.2 Defines a Partial Order -- 1 Remark on Continuity.
TOPICAL NAME USED AS SUBJECT
Electronic digital computers- Circuits
Asynchronous circuits
Logic circuits
Pulse circuits
LIBRARY OF CONGRESS CLASSIFICATION
Class number
E-BOOK
PERSONAL NAME - PRIMARY RESPONSIBILITY
Nystrom, Mika.
PERSONAL NAME - SECONDARY RESPONSIBILITY
Martin, Alain J
ORIGINATING SOURCE
Country
ایران
ELECTRONIC LOCATION AND ACCESS
Host name
1402070683.pdf
Access number
عادی
Compression information
عادی
Date and Hour of Consultation and Access
1402070683.pdf
Bits per second
0
Electronic Format Type
متن
old catalog
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BL
1
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