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عنوان
SystemVerilog for design :

پدید آورنده
by Stuart Sutherland, Simon Davidmann, Peter Flake ; foreword by Phil Moorby

موضوع
Computer simulation,Electronic digital computers-- Design and construction,Verilog (Computer hardware description language)

رده
TK7885
.
7
.
S876
2006

کتابخانه
Center and Library of Islamic Studies in European Languages

محل استقرار
استان: Qom ـ شهر: Qom

Center and Library of Islamic Studies in European Languages

تماس با کتابخانه : 32910706-025

INTERNATIONAL STANDARD BOOK NUMBER

(Number (ISBN
0387333991

NATIONAL BIBLIOGRAPHY NUMBER

Number
dltt

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
SystemVerilog for design :
General Material Designation
[Book]
Other Title Information
a guide to using SystemVerilog for hardware design and modeling /
First Statement of Responsibility
by Stuart Sutherland, Simon Davidmann, Peter Flake ; foreword by Phil Moorby

EDITION STATEMENT

Edition Statement
2nd ed

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
New York :
Name of Publisher, Distributor, etc.
Springer,
Date of Publication, Distribution, etc.
2006

PHYSICAL DESCRIPTION

Specific Material Designation and Extent of Item
xxx, 418 p. :
Other Physical Details
ill. ;
Dimensions
25 cm

INTERNAL BIBLIOGRAPHIES/INDEXES NOTE

Text of Note
Includes bibliographical references and index

TOPICAL NAME USED AS SUBJECT

Computer simulation
Electronic digital computers-- Design and construction
Verilog (Computer hardware description language)

LIBRARY OF CONGRESS CLASSIFICATION

Class number
TK7885
.
7
Book number
.
S876
2006

PERSONAL NAME - PRIMARY RESPONSIBILITY

Sutherland, Stuart,1953-

PERSONAL NAME - ALTERNATIVE RESPONSIBILITY

Davidmann, Simon
Flake, Peter

ORIGINATING SOURCE

Date of Transaction
20061011015427.0

ELECTRONIC LOCATION AND ACCESS

Electronic name
 مطالعه متن کتاب 

[Book]

Y

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