عنوان
پدید آورنده
موضوع
رده
کتابخانه
محل استقرار
INTERNATIONAL STANDARD BOOK NUMBER
(Number (ISBN
9781475766820
(Number (ISBN
9781475766844
NATIONAL BIBLIOGRAPHY NUMBER
Number
b403873
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
SystemVerilog For Design
General Material Designation
[Book]
Other Title Information
A Guide to Using SystemVerilog for Hardware Design and Modeling /
First Statement of Responsibility
by Stuart Sutherland, Simon Davidmann, Peter Flake.
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boston, MA :
Name of Publisher, Distributor, etc.
Imprint: Springer,
Date of Publication, Distribution, etc.
2004.
CONTENTS NOTE
Text of Note
1: Introduction to SystemVerilog -- 2: SystemVerilog Literal Values and Built-in Data Types -- 3: SystemVerilog User-Defined and Enumerated Data Types -- 4: SystemVerilog Arrays, Structures and Unions -- 5: SystemVerilog Procedural Blocks, Tasks and Functions -- 6: SystemVerilog Procedural Statements -- 7: Modeling Finite State Machines with SystemVerilog -- 8: SystemVerilog Design Hierarchy -- 9: SystemVerilog Interfaces -- 10: A Complete Design Modeled with SystemVerilog -- 11: Behavioral and Transaction Level Modeling -- Appendix A: The SystemVerilog Formal Definition (BNF) -- Appendix B: A History of SUPERLOG, The Beginning of SystemVerilog.
0
SUMMARY OR ABSTRACT
Text of Note
SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, SystemVerilog for Design, addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, SystemVerilog for Verification, covers the second aspect of SystemVerilog.
OTHER EDITION IN ANOTHER MEDIUM
International Standard Book Number
9781475766844
PIECE
Title
Springer eBooks
TOPICAL NAME USED AS SUBJECT
Computer engineering.
Computer-aided design.
Engineering.
Systems engineering.
PERSONAL NAME - PRIMARY RESPONSIBILITY
Sutherland, Stuart.
PERSONAL NAME - ALTERNATIVE RESPONSIBILITY
Davidmann, Simon.
Flake, Peter.
CORPORATE BODY NAME - ALTERNATIVE RESPONSIBILITY
SpringerLink (Online service)
ORIGINATING SOURCE
Date of Transaction
20190307162600.0
ELECTRONIC LOCATION AND ACCESS
Electronic name
مطالعه متن کتاب [Book]
Y
