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عنوان
The power of assertions in system verilog

پدید آورنده
Eduard Cerny ... ]et al.[

موضوع
، Verilog )Computer hardware description language(,Verification -- Data processing ، Integrated circuits

رده
TK
7874
.
58
.
P69
2010

کتابخانه
Central Library and Information Center of Ferdowsi University of Mashhad

محل استقرار
استان: Khorasan Razavi ـ شهر: Mashhad

Central Library and Information Center of Ferdowsi University of Mashhad

تماس با کتابخانه : 05138806503

OTHER STANDARD IDENTIFIER

Standard Number
50572

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
The power of assertions in system verilog

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
New York; London
Name of Publisher, Distributor, etc.
Springer
Date of Publication, Distribution, etc.
2010

PHYSICAL DESCRIPTION

Specific Material Designation and Extent of Item
xvii, 544 p. : ill.

NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY

Text of Note
Eduard Cerny ... ]et al.[

TOPICAL NAME USED AS SUBJECT

Entry Element
، Verilog )Computer hardware description language(
Entry Element
Verification -- Data processing ، Integrated circuits

LIBRARY OF CONGRESS CLASSIFICATION

Class number
TK
7874
.
58
.
P69
2010

PERSONAL NAME - PRIMARY RESPONSIBILITY

Relator Code
AU

AU Cerny, Eduard

LOCATION AND CALL NUMBER

Call Number Suffix
CL

Proposal/Bug Report

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