عنوان
پدید آورنده
موضوع
رده
TK7885.7
TK7885
.
7
کتابخانه
محل استقرار
OTHER STANDARD IDENTIFIER
Standard Number
2147
TITLE AND STATEMENT OF RESPONSIBILITY
First Statement of Responsibility
Mehta, Ashok B.
author
Title Proper
SystemVerilog assertions and functional coverage :guide to language, methodology and applications
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
1 online resource )xxxiii, 356 pages( : illustrations
GENERAL NOTES
Text of Note
Includes index
CONTENTS NOTE
Text of Note
Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions Basics )sequence, property, assert(.- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- expect -- assume and formal )static functional( verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-0081 9002 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options )Reference material(
TOPICAL NAME USED AS SUBJECT
Entry Element
، Verilog )Computer hardware description language(
Entry Element
Design and construction ، Electronic digital computers
Entry Element
Verification ، Integrated circuits
Entry Element
، Engineering
Entry Element
، Circuits and Systems
Entry Element
، Electronics and Microelectronics, Instrumentation
Entry Element
، Processor Architectures
DEWEY DECIMAL CLASSIFICATION
Number
621
.
39/2
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK7885
.
7
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
Entry Element
Ashok B. Mehta
TI
LOCATION AND CALL NUMBER
Shelving Form of Title, Author, Author/Title
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