عنوان
پدید آورنده
موضوع
رده
TK 7874 .6 .S62 1996
TK
7874
.
6
.
S62
1996
کتابخانه
محل استقرار
OTHER STANDARD IDENTIFIER
Standard Number
132552
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
زمستان۱۸
.Language of Text, Soundtrack etc
English
TITLE AND STATEMENT OF RESPONSIBILITY
General Material Designation
)50(
First Statement of Responsibility
Smith, Douglas J
Title Proper
HDL chip design: a practical guide for designing, synthesizing, and simulating ASICs and FPGAs using VHDL or Verilog
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Madison
Name of Publisher, Distributor, etc.
Doone Publications
Date of Publication, Distribution, etc.
1996
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xvi, 448 p.: ill.; 29 cm
GENERAL NOTES
Text of Note
Includes index
TOPICAL NAME USED AS SUBJECT
Entry Element
، Application specific integrated circuits-- Computer-aided design
Entry Element
، Field programmable gate arrays-- Computer-aided design
Entry Element
، Logic design-- Data processing
Entry Element
، VHDL )Computer hardware description language(
Entry Element
، Verilog )Computer hardware description language(
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7874
.
6
.
S62
1996
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
Entry Element
Douglas J. Smith
TI
LOCATION AND CALL NUMBER
Shelving Form of Title, Author, Author/Title
05
