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عنوان
ظ…ط¨ط§ظ†غŒ ظ…ط¯ط§ط± ظ…ظ†ط·ظ‚غŒ ط¨ط§ ظ†ط±ظ… ط§ظپط²ط§ط± Verilog

پدید آورنده
/ ط§ط³طھظپظ† ط¨ط±ط§ظˆظ†ظ¬ ط²ظˆظ†ع©ظˆ ظˆط±ط§ظ†ط³غŒط¬,â€ڈ‫ط¹ظ†ظˆط§ظ† ط§طµظ„غŒ: .Fundamentals of digital logic with Verilog design,3 nd, c2014‬,ط¨ط±ط§ظˆظ†,Braun

موضوع
â€ڈ‫ظ…ط¯ط§ط±ظ‡ط§غŒ ظ…ظ†ط·ظ‚غŒâ€¬â€¬,Logic circuits,â€ڈ‫ظˆط±غŒظ„ط§ع¯ (ط²ط¨ط§ظ† طھظˆطµغŒظپغŒ ط³ط®طھ‌ط§ظپط²ط§ط± ع©ط§ظ…ظ¾غŒظˆطھط±)‬‬,Verilog (Computer hardware description language),ط·ط±ط§ط­غŒ ط¨ظ‡ ع©ظ…ع© ع©ط§ظ…ظ¾غŒظˆطھط±,Computer-aided design, -- ط¯ط§ط¯ظ‡â€Œظ¾ط±ط¯ط§ط²غŒ, -- Data processing,a01,a01,a02,a02,a03,a03

رده
â€
ڈ
‫‬‭
TK
غ
·
غ
¸
غ
¶
غ
¸ ‭
/
ط
¨
غ
´
ظ
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غ
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±
غ
³
غ
¹
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´â€¬

کتابخانه
Farabi Faculty Library, University of Tehran

محل استقرار
استان: Qom ـ شهر: Qom

Farabi Faculty Library, University of Tehran

تماس با کتابخانه : 02536166323

INTERNATIONAL STANDARD BOOK NUMBER

(Number (ISBN
â€ڈ‫‬‭978-964-410-359-9

NATIONAL BIBLIOGRAPHY NUMBER

Country Code
IR
Number
غµغ²غ¸غ´غ²

LANGUAGE OF THE ITEM

.Language of Text, Soundtrack etc
per
Language of Original Work
eng

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
ظ…ط¨ط§ظ†غŒ ظ…ط¯ط§ط± ظ…ظ†ط·ظ‚غŒ ط¨ط§ ظ†ط±ظ… ط§ظپط²ط§ط± Verilog
General Material Designation
[ع©طھط§ط¨]
First Statement of Responsibility
/ ط§ط³طھظپظ† ط¨ط±ط§ظˆظ†ظ¬ ط²ظˆظ†ع©ظˆ ظˆط±ط§ظ†ط³غŒط¬
Subsequent Statement of Responsibility
ط› ظ…طھط±ط¬ظ… ط¹ظ„غŒط±ط¶ط§ ط²ط§ط±ط¹â€Œظ¾ظˆط±.

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
طھظ‡ط±ط§ظ†
Address of Publisher, Distributor, etc.
طھظ„ظپظ† ظ†ط§ط´ط± :غ¶غ¶غ´غ¶غµغ¶غ·غ´ طŒط¢ط¯ط±ط³ ظ†ط§ط´ط± :ظ…غŒط¯ط§ظ† ط§ظ†ظ‚ظ„ط§ط¨. ط® ظ…ظ†غŒط±غŒ ط¬ط§ظˆغŒط¯طŒ ط¨ظ† ط¨ط³طھ ظ…ط¨غŒظ† طŒ ظ¾ظ„ط§ع© غ¶
Name of Publisher, Distributor, etc.
: ظ†ط´ط± ظ†طµ
Date of Publication, Distribution, etc.
â€ڈ‫ظ¬ غ±غ³غ¹غ´.

PHYSICAL DESCRIPTION

Specific Material Designation and Extent of Item
â€ڈ‫غ·غ±غ´ طµ.‬
Other Physical Details
: ظ…طµظˆط± (ط±ظ†ع¯غŒ)طŒ ط¬ط¯ظˆظ„(ط¨ط®ط´غŒ ط±ظ†ع¯غŒ)طŒ ظ†ظ…ظˆط¯ط§ط±ظ¬ ط¹ع©ط³.

NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY

Text of Note
â€ڈ‫ط¹ظ†ظˆط§ظ† ط§طµظ„غŒ: .Fundamentals of digital logic with Verilog design,3 nd, c2014‬

INTERNAL BIBLIOGRAPHIES/INDEXES NOTE

Text of Note
ظ†ظ…ط§غŒظ‡.

TOPICAL NAME USED AS SUBJECT

Entry Element
â€ڈ‫ظ…ط¯ط§ط±ظ‡ط§غŒ ظ…ظ†ط·ظ‚غŒâ€¬â€¬
Entry Element
Logic circuits
Entry Element
â€ڈ‫ظˆط±غŒظ„ط§ع¯ (ط²ط¨ط§ظ† طھظˆطµغŒظپغŒ ط³ط®طھ‌ط§ظپط²ط§ط± ع©ط§ظ…ظ¾غŒظˆطھط±)‬‬
Entry Element
Verilog (Computer hardware description language)
Entry Element
ط·ط±ط§ط­غŒ ط¨ظ‡ ع©ظ…ع© ع©ط§ظ…ظ¾غŒظˆطھط±
Entry Element
Computer-aided design
Topical Subdivision
-- ط¯ط§ط¯ظ‡â€Œظ¾ط±ط¯ط§ط²غŒ
Topical Subdivision
-- Data processing
a01
a01
a02
a02
a03
a03

LIBRARY OF CONGRESS CLASSIFICATION

Class number
â€
ڈ
‫‬‭
TK
غ
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Book number
‭
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ط
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PERSONAL NAME - PRIMARY RESPONSIBILITY

Entry Element
ط¨ط±ط§ظˆظ†
Entry Element
Braun
Part of Name Other than Entry Element
طŒ ط§ط³طھغŒظˆظ†
Part of Name Other than Entry Element
, Stephen
Dates
طŒ â€ڈ‫غ±غ¹غµغ· -â€ڈ ظ….‬
a01
a01
ba

PERSONAL NAME - ALTERNATIVE RESPONSIBILITY

Entry Element
ظˆط±ط§ظ†ط³غŒع†
Entry Element
Vranesic
Part of Name Other than Entry Element
طŒ ط²ظˆظˆظ†ع©ظˆ ط¬غŒ.
Part of Name Other than Entry Element
, Zvonko G.
a01
a01
ba

PERSONAL NAME - SECONDARY RESPONSIBILITY

Entry Element
ط²ط§ط±ط¹â€Œظ¾â€چظˆط±
Part of Name Other than Entry Element
طŒ ط¹â€چظ„â€چغŒط±ط¶ط§
Dates
طŒâ€ڈ‫ غ±غ³غ´غ° - â€ڈ
Relator Code
طŒ ظ…طھط±ط¬ظ…

ORIGINATING SOURCE

Country
IR
Agency
ط¯ط§ظ†ط´ع¯ط§ظ‡ طھظ‡ط±ط§ظ†. ع©طھط§ط¨ط®ط§ظ†ظ‡ ظ¾ط±ط¯غŒط³ ظپط§ط±ط§ط¨غŒ
Date of Transaction
20231111

ELECTRONIC LOCATION AND ACCESS

Path
manti.pdf
b2fb17e3-3f3b-4c4a-aab4-19674abe62f6

BF
241516
1

a
Y

Y

â€ڈ‫ظ…ط¯ط§ط±ظ‡ط§غŒ ظ…ظ†ط·ظ‚غŒâ€¬â€¬ -- ط·ط±ط­ ظˆ ط³ط§ط®طھظ…ط§ظ† -- ط¯ط§ط¯ظ‡â€Œظ¾ط±ط¯ط§ط²غŒ
Logic circuits -- Design and construction -- Data processing

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